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nt 68275 iic bus controlled on - screen display 1 v1.0 features n i i c bus interface with slave address $7a (transmitter) & $7b (receiver) n horizontal frequency range: 30khz ~ 1 5 0khz * n flexible display resolution up to 1524 dots/row n internal pll generates a stable and wide - ranged system clock ( 120 mhz) * n osd screen consist character array of 15 rows by 30 columns n programmable vertical and horizontal position for osd displaying center n total of 528* rom fonts i ncluding 512* standard & 16 multi - color rom fonts. n 12 x 18 dot matrix per character n 8 - color selec tion for each character n 7 - color selection for each character background n character/symbol blinking, shadowing & bordering display effect n double character height and width for each row n programmable height of character/symbol display n row to row spacing co ntrol to avoid expansion distortion n four programmable windows with overlapping capability and shadowing effect n color setting for windows ? background and character shadowing & bordering n fade - in/out effect of osd screen display n hsync & vsync input polari ty selectable general description NT68275 is designed for displaying symbols and characters onto a crt monitor. its operation is controlled by a micro controller with an i i c bus interface. by sending proper data and command s to NT68275, it can carry o ut the full screen display automatically with the time base generated by an on - chip pll circuit. there are many functions provided by this chip to fully support user application s , such as: adjustment of the position of osd windows , built - in 512* rom & 16 multi - color fonts, variable character height with row - to - row spacing adjustment, 8 color selections & 7 background color controls for each character, double height/width controls for each row, 4 overlapping window available with color & size controls, size controls for each window shadowing, color selection for windows? shadowing & character shadowing/ bordering , fade - in/out display effect , etc. the ? * ? sign denote s that feature different from nt6827.
NT68275 2 block diagram i 2 c bus receiver scl sda vsync vflb hsync hflb vpol hpol display memory contol reg. rom font 12 * 18 output control r/g/b fbkg *pwm/int power system avcc power on low voltage reset timing generator dvcc agnd dgnd vertical control pll circuit rp vco horizontal control bus control buffer display effect color control test circuit
NT68275 3 pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 16 15 14 13 agnd vco rp avcc hflb n.c. sda scl dgnd r g b fbkg *pwmck/int vflb dvcc NT68275
NT68275 4 pin description NT68275 name i/o/p/r function 1 agnd p analog ground 2 vco - voltage i/p to control oscillator 3 rp - bias resistor. u sed to bias internal vco to resonate at specific dot frequency 4 avcc p analog power supply (5 v typ . ) 5 hflb i horizontal fly - back input (schmitt trigger buffer) 6 n.c. - - 7 sda i sda pin of iic bus (schmitt trigger buffer) with internal 100k ohm pulled - high resistance 8 scl i scl pin of iic bus (schmitt trigger buffer) with internal 100k ohm pulled - high resistance 9 dvcc p digital power supply (5 v typ . ) 10 vflb i vertical fly - back input (schmitt trigger buffer) 11 *pwmc k/int o pwm output or intensity output 12 fbkg o fast blanking output. u sed to cut off external r, g, b signals. 13 b o blue color output with push - pull output structure 14 g o green color output with push - pull output structure 15 r o red color output with push - pull output structure 16 dg nd p digital ground
NT68275 5 dc/ac absolute maximum ratings* recommended operating conditions vcc (measured to gnd) . . . . . . . . . . . . 4. 7 5v to 5. 2 5v operating temperature . . . . . . . . . . . . . 0 to +70 0c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. exposed to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (vdd = 5v, tamb = 25 c) symbol parameter min. typ. max. unit notes vcc supply voltage 4. 7 5 5 5 . 2 5 v dc characteristic symbol parameter min. typ. max. unit notes i dd operating current 22 25 ma no loading vih1 input high voltage 2 v vflb, hflb with schmitt trigger buffer vil1 input low voltage 0.8 v vflb, hflb schmitt trigger buffer vih2 iic bus input high voltage 3 v vil2 iic bus input low voltage 1.5 v scl, sda idrive1 driving current of r, g, b, fbkg, hfton output pins at 2.4v output voltage 80 ma isink1 sinking current of r, g, b, fbkg, hfton output pins at 0.4v output volt age 20 ma ileak leakage current of r, g, b, fbkg pins at hi - z state 10 ua measured at 2.5v state iiicl iic bus ou t put sink current 5 ma viicoutl = 0.4v vth input threshold voltage at hflb & vflb 1.8 2.0 2.2 v vstih schmitt trigger input hig h voltage 1.7 2 v vstil schmitt trigger input low voltage 0.8 1.1 v refer figure 1 iin input current of hsync, vsync, sda, scl pins - 10 +10 ua schmitt trigger buffer
NT68275 6 1.1v 1.7v vh vl output state input voltage figure 1 . schmitt trigger diagram ac charact eristic symbol parameter min. typ. max. unit notes fhfy horizontal fly - back frequency 30 * 1 5 0 khz 5 v vhfly horizontal fly - back input 0 v thflymin minimum pulse width of horizontal fly - back 0.7 us thflymax maximum pulse width of horizonta l fly - back 5.5 us fvfy vertical fly - back frequency 50 * 200 hz 5 v vvfly vertical fly - back input 0 v tvflymin minimum pulse width of vertical fly - back 20 us tvflymax maximum pulse width of vertical fly - back 1 ms hflb 2.0 v thwidth 0 v 5 v vflb 2.0 v tvwidth 0 v 5 v figure 2 . h/v fly - back signal
NT68275 7
NT68275 8 i i c bus - slave transmitter & receiver (slave address: $7a & $7b) table 1 . i ic bus symbol parameter min. typ. max. unit notes fmaxcl maximum scl clock frequency 100 khz vil input low voltage - 0.5 1.5 v vih input high voltage 3.0 5.5 v tlow low period of scl clock 4.7 us thigh high period of scl clock 4.0 us tsudat data setup time 250 ns thddat data hold time 300 ns tiicr rise time of iic bus 1000 ns tiicf fall time of iic bus 300 ns tsusta setup time for repeated start condition 1.3 us thdsta hold time for start condition 4.0 us tsusta setup time for start condition 4.7 us tsusto setup time for stop condition 4.0 us scl, sda tiicbuf time iic bus must be free before next new transmission can start 4.7 us iiicl iic bus sink current 4 5 ma viicoutl = 0.4 v tfilter input filter s pike s uppression 100 ns scl, sda see also i i c table control and i i c sub address control scl sda tiicbuf thdsta tsudat thigh tiicr tiicf thddat tlow stop start tsusta thdsta stop tsusto start figure 3 . iic bus timing
NT68275 9 memory map 29 14 0 7 0 7 row attribute register row attribute register row 7 0 30 column 0 0 0 display register fonts address $00-$ff 7 figure 4 - 1 . memory map of display register (row 0 ? 14) 0 29 14 0 0 7 0 7 column row character attribute register character attribute register figure 4 - 2 . memory map of attribute register (row 0 ? 14)
NT68275 10 row 0 15 0 7 0 7 window 1-4 control register column 11 window1 - window4 osd screen control 12 22 0 7 0 7 osd screen control register 23 0 7 reset flag control register figure 4 - 3 . memory map of control register (row 15)
NT68275 11 list of control registers: (1) display register: row 0 ? 14 , column 0 ? 29 8 7 6 5 4 3 2 1 0 row 0 - 14 column 0 - 29 * page msb lsb font?s address $00 - $1ff bit 8 : * page - this bit will address the page 1 rom font area by bit 7 - 0 of this control register. otherwise, it will address page 0. this can be set by the bit5 column data at iic bus transmission. refer to f igure 8 - 1 & 8 - 3 for rom font area. bit 7 - 0 : th ese eight bits will address one of the 256 characters/ symbols residing in the character rom fonts. note that if user set s mcfont bit (row 15, column 22) to ?1?, the 0 ~ 256 will address standard rom fonts, and if clear ed to ?0? , the 0 ~ 239 will address standard rom fonts & 240 ~ 255, multi - color rom fonts. (2) character attribute register: row 0 ? 14, column 0 ? 29 7 6 5 4 3 2 1 0 row 0 - 14 column 0 - 29 bkr bkg bkb blink r g b character attribute control bit 6 - 4: bkr/g/b - these three bits define the color attribute of the background for the corresponding character/symbol. if all three bits are cleared, no background will be displayed. refer to the tab 3 for the color selections. bit 3: blink - this bit enable s the blinking effect of the corresponding character/symbol with this bit set to ?1?. the blinking frequency is approximately 1hz with a fifty - fifty duty cycle at 80hz vertical sync frequency. bit 2 - 0: r/g/b - these three bits define the color attribute o f the corresponding character/symbol. refer to the tab 2 for the color selections. tab 2 . character/window color selection color r g b black 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 tab 3 . charac ter/window background color selection color r g b no background 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1
nt 68275 iic bus controlled on - screen display 12 v1.0
NT68275 13 (3) row attribute register: row 0 ? 14, column 30 7 6 5 4 3 2 1 0 row 0 - 14 column 3 0 *rint dbh dbw row?s attribute control bit 1: dbh ? this bit controls the height of the displayed character/symbol. when this bit is set, the character/symbol is displayed in double height. bit 0: dbw ? this bit controls the width of the displa yed character/symbol. when this bit is set, the character/symbol is displayed in double width. bit 2 : * rint ? row intensity, this bit controls the intensity of the corresponding row .by setting this bit to 1 , t he int pin will go high when the characters of this row are displayed. see figure 5.
NT68275 14 (4) window 1 registers: row 15, column 0 7 6 5 4 3 2 1 0 row start address row end address row 15 column 0 msb lsb msb lsb window 1 row s ize control bit 7 - 4: these bits determine the row start position of window 1on the 15*30 osd screen. bit 3 - 0: these bits determine the row end position of window 1on the 15*30 osd screen. 7 6 5 4 3 2 1 0 colum n start address row 15 column 1 msb lsb winen *wint shad window1 column size control & attribute control bit 7 - 3: these bits determine the column start position of window 1 on the 15*30 osd screen. bit 2: winen - this bit enables window 1 when it is set. the default value is 0 after power on. bit 1 : * win t - window intensity . this bit controls the intensity of window 1 .by setting this bit to 1, the int pin will go high while displaying w indow 1 and characters inside the windo w. see figure 5. bit 0: shad - this bit enable s the shadowing on the window when it is set to ?1?. the default value is 0 after power on. 7 6 5 4 3 2 1 0 column end address row 15 column 2 msb lsb r g b window 1 colum n size control & attribute control bit 7 - 3 : these bits determine the column end position of window 1on the 15*30 osd screen. bit 2 - 0 : r/g/b ? these bits control the background color of window 1. refer to table for color selection. note : window 1 control registers occupy column 0 - 2 of row 15, window 2 from column 3 - 5, window 3 from 6 - 8 and window 4 from 9 - 11. the function of window 2 - 4 control registers is the same as window 1. window 1 has the highest priority, and the window 4, the le ast. the higher priority color will take over on the overlap window area. if the start address of the row/column is greater than the end address, the window will not be displayed . out of range setting (over 15 row s or 30 column s range) will cause ab normal operation.
NT68275 15 osd screen position control registers: row 15, column 12 - 13 7 6 5 4 3 2 1 0 vpos row 15 column 12 msb lsb vertical position adjustment bit 7 - 0 : vpos - these bits determine the vertical starting position for the cha racter display. it is the vertical delay starting from the leading edge of vflb. the unit of this setting is 4 horizontal lines and the equation is defined as bel ow: vertical delay = (vpos * 4 +1) * horizontal line . the default value of it is 4 ($04) aft er power on. 7 6 5 4 3 2 1 0 hpos row 15 column 13 msb lsb horizontal position adjustment bit 7 - 0: hpos ? these bits determine the horizontal starting position for the character display. it is the horizontal delay starting from the leadi ng edge of hflb. the unit of this setting is 6 dots movement shift to right on the monitor screen and the equation is defined as bel ow: horizontal delay = (hpos * 6 + 49) / p.r. where the p.r. (pixel rate) is defined by the hdr & horizontal frequen cy. p.r. (pixel rate) = hdr * 12 * freq hflb refer the hdr control register at row 15 / column 15 for the p.r. setting. the default value of these bit is 15 ($ 0f) after power on.
NT68275 16 (5) character height control: row 15, column 14 7 6 5 4 3 2 1 0 row 1 5 column 14 crh6 crh5 crh4 crh3 crh2 crh1 crh0 character?s height control bit 6 - 0 : crh6 - crh0 - these bits determine the displayed character height. character, original 12 by 18 font matrix, can be expanded from 18 to 71 lines. refer to the table bel ow. all of these bits will be cleared to ?0? after power on. if the setting value of ch0 ? ch6 is great than 17 , the algorithm will repeat at most 17 lines. tab 4 . lines expanded control crh6 ~ crh0 lines inserted crh6 = ? 1 ? , crh5 = ? 1 ? all 18 lines repeat twice crh6 = ? 1 ? , crh5 = ? 0 ? all 18 lines repeat once crh6 = ? 0 ? , crh5 = ? x ? repeat at most 17 lines crh4 = ? 1 ? insert 16 lines crh3 = ? 1 ? insert 8 lines crh2 = ? 1 ? insert 4 lines crh1 = ? 1 ? insert 2 lines crh0 = ? 1 ? insert 1 lines tab 5. lines expanded position repeat position no. of lines inserted 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 insert 1 lines ! insert 2 lines ! ! insert 4 lines ! ! ! ! insert 8 lines ! ! ! ! ! ! ! ! insert 16 lines ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! insert 17 lines ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !
NT68275 17 (6) flexible display control register : row 15 , column 15 7 6 5 4 3 2 1 0 hdr row 15 column 15 msb lsb horizontal display resolution control bit 6 - 0 : hdr - these bits determine the resolution of the horizontal display line. the unit of this setting is twelve dots ( one character) . with t otal 92 steps ( $24 ~ $ 7f: 36 ~ 127 steps; value can no t be smaller than 36 anytime.), user can adjust the resolution from 36 to 127 characters on each horizontal line. note that the resolution adjustment must cooperate with the vco setting at row 15 / column 18 control register. refer to the table of the control register at row 15 / column 18. the default value of it is 40 after power on. (7) osd row to row space control register : row 15 , column 16 7 6 5 4 3 2 1 0 r2rspace row 15 column 16 msb lsb row to row space adjustment bit 4 - 0 : r2rspace - these bits define the row - to - row spacing in unit s of horizontal line s . e xtra lines defined by this 5 - bit value will be appended for each display row. the default value is 0 after power on and there is no extra line inserted between row s. all of these bits will be cleared to ?0? after power on. (8) input/output control register : row 15 , column 17 7 6 5 4 3 2 1 0 row 15 col umn 17 osden bsen shadow fade blank clrwin clrdspr fbkgc osd screen control 1 bit 7 : osden ? this bit will enable the osd circuit when it is set to ?1?. the default value is ?0? after power on. bit 6 : bsen ? this bit will enable the bordering an d shadowing effect when it is set to ?1?. the default value is ?0? after power on. bit 5 : shadow ? when the bsen set to ?1? , it will enable the shadowing effect when this bit set to ?1?, too. otherwise, it will enable the bordering effec t as this bit is cleared to ?0?. the default value is ?0? after power on. bit 4 : fade - this bit enable s the fade - in/out effect when the osd screen is turned on by setting from osden = ?0? to ?1? or turned off by setting from osden = ?1? to ?0? . the fade - in/out effect will be completed about 0.5 second s when the input vsync is 60 hz. the default value of this bit is ?0? after power on . bit 3 : blank ? this bit will force the fbkg pin to output high when this bit & the fbkgop are bit set to ?1?. otherwise , the fbkg pin will output low when this bit is set to ?1? & fbkgop bit set to ?0?. the default value of this bit is ?0? after power on . bit 2 : clrwin ? this bit will clear all windows? winen control bit as it is set t o ?1?. the default value of this bit is ?0? after power on . bit 1 : clrdspr ? this bit will clear all of the content in the display registers and r, g, g, blnk bit in the character attribute registers when it is set to ?1?. the default value of this bit is ?0? after power on .
NT68275 18 bit 0 : fbkgc - it determines the configuration of fbkg output pin. when it is cleared , the fbkg pin will output high during displaying characters or windows. otherwise, it will output high only during displaying characters. the de fault value of this bit is ?0? after power on.
NT68275 19 7 6 5 4 3 2 1 0 row 15 column 18 rgbf fbkgop * pwm /int dbounce hpol vpol vco1 vco0 osd screen control 2 bit 7 : rgbf - this bit controls the driving state of output pins, r, g, b and fbkg when t he osd is disabled. after power on, this bit is cleared to ?0? and all of the r, g, b and fbkg pins output a high impedance state while the osd is being disabled. if this bit is set to ?1? , the r, g, b output pins will drive low, fbkg pin dr ive high or low depend on fbkgop (if fbkgop= 0, drive high. if fbkgop=1, drive low) while osd being disabled. bit 6 : fbkgop - this bit selects the polarity of the output signal of fbkg pin. this signal is active low when the user clear s thi s bit. otherwise , active high set this bit . refer the figure 5 bel ow for the fbkg output timing . the default value is ?1? after power on. bit 5 : * pwm /int - this bit selects the output option to pwm/ int pin. this bit will enable the pwm clock outpu t as it is set to ?1?. otherwise, it will select the int option. refer the figure 5 bellow for the int output timing. the default value is ?0? after power on. bit 4 : dbounce - this bit is to activate the debounce circuit of horizontal and vertical scan. it is to prevent from the osd screen shaking when user adjusts the horizontal phase or vertical position. this bit will be cleared after power on. bit 3 : hpol - this bit selects the polarity of the input signal of horizontal sync (hflb pin) . if the input sync signal is negative polarity, user must clear this bit. otherwise , set this bit to ?1? to accept the positive polarity signal. after power on, this bit is cleared to ?0? and it will accept negative polarity sync signal. bit 2 : vpol - this bit selects the polarity of the input signal of vertical sync ( vflb pin) . if the input sync signal is negative polarity, user must clear this bit. otherwise , set this bit to ?1? to accept the positive polarity signal. after power on, this bit is cleared to ?0? and it will accept negative polarity sync signal. bit 1 - 0 : vco1/0 ? these bits select the vco frequency range when user set the horizontal display resolution flexibly. it is related to the horizontal display resolution and user must set the control register at row15 / column15 properly. the default value is vco1=0 & vco0=0 after power on state. the relationship between vco1/0 and display resolution is list bel ow: tab 6 . p.r. (pixel rate) = hdr * 12 * freq hflb section vco1 vco0 vco freq. min vco freq. max unit p.r. limit hflb freq. limit freq1 0 0 * 6 * 1 3 freq2 0 1 * 1 4 *28 freq3 1 0 *29 *60 freq4 1 1 *61 *120 mhz min < p.r. < max (min / hdr*12) < freq hflb < max / (hdr*12) if there are no signal s at h flb input, the pll will generate an approximate 2.5 mhz clock to ensure the proper operation of the iic bus and other control registers.
NT68275 20 figure 5 . * fgbk & int output timing window backgroun window backgroun cha racter b ackgroun cha racter backgroun ch aracter shadowin fbkgc bit = ?0? wint = 0 fbkgc bit = ?1? wint = 1 fbk int1 rint=1 rint=0 int1 int2 int2
NT68275 21 (10) color selection for shadowing/bordering effe ct : row 15, column 19 7 6 5 4 3 2 1 0 row 15 column 19 winr wing winb chr chg chb shadowing/bordering color control bit 6 - 4 : winr/g/b ? these bits control the shadowing color of window 1 - 4. refer to table 7 for color selection . all of these bits will be cleared to ?0? after power on. bit 2 - 0 : chr/g/b ? these bits control the shadowing/bordering color of each character . refer to table 7 for color selection. all of these bits will be cleared to ?0? after power on. tab 7 c haracter/windows? shadowing color selection color r g b black 0 0 0 blue 0 0 1 green 0 1 0 cyan 0 1 1 red 1 0 0 magenta 1 0 1 yellow 1 1 0 white 1 1 1 (11) multi - color font control : row 15, column 20 7 6 5 4 3 2 1 0 row 15 column 20 mcfont multi - color font control bit 0: mcfont ? this bit will enable multi - color fonts addressed from 240 to 255 when it is set to ?1?. the default value is ?0? after power on and enable standard rom fonts.
NT68275 22 (12) adjustments of width & height for windows? shadowing : row 15, column 21, 22 7 6 5 4 3 2 1 0 row 15 column 21 w4wd1 w4wd0 w3wd1 w3wd0 w2wd1 w2wd0 w1wd1 w1wd0 setting of windows? shadowing width wxwd1/0 ? th is will determine the size of window?s width when the shad bit of windows control register ( row 15 column 1,4,7,10 ) be set to ?1?. the default value s are ?0 0 ? after power on. refer to the tab be low for the size adjustments. wxwd1/0 ( 0 , 0 ) ( 0 , 1 ) ( 1 , 0 ) ( 1 , 1 ) units window shadowing width 2 4 6 8 pixels 7 6 5 4 3 2 1 0 row 15 column 22 w4ht1 w4ht0 w3ht1 w3ht0 w2ht1 w2ht0 w1ht1 w1ht0 setting of window shadowing height wxht1/0 ? these bit will determine the window height when the shad bit of the window control register (row 15 column 1,4,7,10) is set to ?1?. the default value s are ?0 0 ? after power on. refer to the tab be low for the size adjustments. wxht1/0 ( 0 , 0 ) ( 0 , 1 ) ( 1 , 0 ) ( 1 , 1 ) units window shadowing height 2 4 6 8 pixels
NT68275 23 (13) reset flag control registers 7 6 5 4 3 2 1 0 row 15 column 23 resetflg bit 1 : restflg ? a system reset will clear this bit. user can set this bit first and detect if internal reset circuit has reset the system . this bit can be read back through iic bus by external master device, for example mcu. the other bits a re reserved. (14) r eserved control register : row 15, column 24 & 31 7 6 5 4 3 2 1 0 row 15 column 24 reserved this control register is reserved and any data can not be written into this register. 7 6 5 4 3 2 1 0 row 15 column 31 reserved this control register is reserved and any data can not be written into this register. iic bus read mode operation : 3 ---- 1 bytes data ---- 4 type (1) (2) (3) (4) (a) start condition osd slave address ?$7b? row15 column 2 3 data stop condition 8 bits 8 bits user must read these bytes of data sequentially and can abort transmission by send ing nak (no acknowledge), repeat start condition or stop condition. every time user send s the start condition ( including repe at start ) and slave address $7b , the nt682 75 will respond ack and then transmit the first byte ( content of row 5 column 3 register) . it is prohibited to read more than 1 byte of data.
NT68275 24 i i c bus communication: figure 6 shows the iic bus transmission format. the master initiates a transmission routine by generating a start condition, followed by a slave address byte. once the address is properly identified, the slave will respond with an ac - knowledge signal by pulling the sda line low during the ninth scl clock. each data byte which then follows must be eight bits long, plus the acknowledge bit, to make up nine bits together. this acknoledge bit is sent by NT68275 at write mode operation and by master, at read mode. in the write mod e, appropriate row and column address information and display data can be downloaded sequentially from the master in one of the three transmission formats described in figure 6 access register operation. in the read mode, the content in some control reg isters can be transferred to the master. in the cases of no acknowledge or completion of data transfer, the master will generate a stop condition to terminate the transmission routine. note that the osd_en bit must be set after all the display information has been sent in order to activate the displaying circuitry of NT68275, so that the received in - formation can then be displayed. write operation of the control registers: after the proper identification by the receiving device, a data train of arbitr ary length is transmitted from the master. there are three transmission formats from (a) to (c) as stated bel ow the t iming section . the data train in each sequence consists of row address, column address and data. in format (a), data must be preceded w ith the corresponding row address and column address. this format is particularly suitable for updating small amounts of data between different rows. however, if the current information byte has the same row address as the one before, format (b) is recomme nded. for a full screen pattern change which requires a massive information update, or during power up situation, most of the row and column addresses on either (a) or (b) format will appear to be redundant. a more efficient data transmission format (c) sh ould be applied. this sends the starting row and column addresses once only, and then treats all subsequent data as display information. the row and column addresses will be automatically incremented internally for each display information data from the st arting location. to differentiate the row and column addresses when transferring data from master, the msb (most significant bit) is set as in tab 8 transmission: ?1? represent row, while ?0? for column address. furthermore, to distinguish the column addr ess between format (a), (b) and (c), the sixth bit of the column address is set to ?1? , which represents format (c), and a ?0? for format (a) or (b). there is some limitation on using mix - formats during a single transmission. it is permissible to change t he format from (a) to (b), or from (a) to (c), or from (b) to (a), but not from (c) back to (a) or (b).
NT68275 25 i i c bus write operation timing : figure . 6 access register write operation 3 --------------- repeat -------------- 4 type (1) (2) (3) (4) (5) (3) (4) (5) (6) (a) start condition osd slave address ?$7a? row address data column address data information data row address data column address data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 3 ------ repeat ----- 4 type (1) (2) (3) (4) (5) (4) (5) (6) (b) start condition osd slave address ?$7a? row address data column address data information data column address data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 3 repeat 4 type (1) (2) (3) (4) (5) (5) (5) (6) (c) start condition osd slave address ?$7a? row address data column address data information data information data information data ? stop condition 8 bits 8 bits 8 bits 8 bits 8 b its 8 bits tab 8 . address data transmission for registers item no address b7 b6 b5 b4 b3 b2 b1 b0 type 1 row 1 0 0 x r3 r2 r1 r0 (a),(b),(c) 2 column 0 0 * page c4 c3 c2 c1 c0 (a),(b) 3 column 0 1 * page c4 c3 c2 c1 c0 (c) display register 4 inf ormation data d7 d6 d5 d4 d3 d2 d1 d0 5 row 1 0 1 x r3 r2 r1 r0 (a),(b),(c) 6 column 0 0 x c4 c3 c2 c1 c0 (a),(b) 7 column 0 1 x c4 c3 c2 c1 c0 (c) attribute / control register 8 information data d7 d6 d5 d4 d3 d2 d1 d0 * the page bit will identi fy the page number of rom font area. if this bit is set ?0?, the following information data will address the page 0 rom font area. otherwise, it will address the page 1.
NT68275 26 read operation of the control registers : not all control registers can be read o ut by the master via iic bus of read mode. bellow listed , after the proper identification of slave address ($ 7b) by the NT68275 , 1 byte data train is transmitted to the master. item register bytes 1 row 15 column 23 contro l register 1 i i c bus read operation timing: figure 7 . access register read operation 3 ---- 1 bytes data ---- 4 type (1) (2) (3) (4) (a) start condition osd slave address ?$7b? row15 column 23 data stop condition 8 bits 8 bits user must read these bytes of data sequentially and can abort transmission by send ing nak (no acknowledge) , repeat start condition or stop condition. every time user send s the start condition (including repeat start) and slave address $ 7b, the nt682 75 wil l respond ack and then transmit first byte ( content of row 15 column 23 register) . it is prohibited to read more than 1 byte of data.
NT68275 27 font access: ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0 a ) ( 0 b ) ( 0 c ) ( 0 d ) ( 0 e ) ( 0 f ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1 a ) ( 1 b ) ( 1 c ) ( 1 d ) ( 1 e ) ( 1 f ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 2 a ) ( 2 b ) ( 2 c ) ( 2 d ) ( 2 e ) ( 2 f ) ( d0 ) ( d1 ) ( d2 ) ( d3 ) ( d4 ) ( d5 ) ( d6 ) ( d7 ) ( d8 ) ( d9 ) ( da ) ( db ) ( dc ) ( dd ) ( de ) ( df ) ( e0 ) ( e1 ) ( e2 ) ( e3 ) ( e4 ) ( e5 ) ( e6 ) ( e7 ) ( e8 ) ( e9 ) ( ea ) ( eb ) ( ec ) ( ed ) ( ee ) ( ef ) ( f0 ) ( f1 ) ( f2 ) ( f3 ) ( f4 ) ( f5 ) ( f6 ) ( f7 ) ( f8 ) ( f9 ) ( fa ) ( fb ) ( fc ) ( fd ) ( fe ) ( ff ) . . . rom fonts figure 8 - 1 . page 0 including 256 standard rom f ont configuration ( 00 ) ( 01 ) ( 02 ) ( 03 ) ( 04 ) ( 05 ) ( 06 ) ( 07 ) ( 08 ) ( 09 ) ( 0 a ) ( 0 b ) ( 0 c ) ( 0 d ) ( 0 e ) ( 0 f ) (10 ) ( 11 ) ( 12 ) ( 13 ) ( 14 ) ( 15 ) ( 16 ) ( 17 ) ( 18 ) ( 19 ) ( 1 a ) ( 1 b ) ( 1 c ) ( 1 d ) ( 1 e ) ( 1 f ) ( 20 ) ( 21 ) ( 22 ) ( 23 ) ( 24 ) ( 25 ) ( 26 ) ( 27 ) ( 28 ) ( 29 ) ( 2 a ) ( 2 b ) ( 2 c ) ( 2 d ) ( 2 e ) ( 2 f ) ( d0 ) ( d1 ) ( d2 ) ( d3 ) ( d4 ) ( d5 ) ( d6 ) ( d7 ) ( d8 ) ( d9 ) ( da ) ( db ) ( dc ) ( dd ) ( de ) ( df ) ( e0 ) ( e1 ) ( e2 ) ( e3 ) ( e4 ) ( e5 ) ( e6 ) ( e7 ) ( e8 ) ( e9 ) ( ea ) ( eb ) ( ec ) ( ed ) ( ee ) ( ef ) ( f0 ) ( f1 ) ( f2 ) ( f3 ) ( f4 ) ( f5 ) ( f6 ) ( f7 ) ( f8 ) ( f9 ) ( fa ) ( fb ) ( fc ) ( fd ) ( fe ) ( ff ) . . . rom fonts multi-color rom fonts figure 8 - 2 . page 0 including 240 standard & 16 multi - color rom font configuration
NT68275 28 (100 ) ( 101 ) ( 102 ) ( 103 ) (104 ) ( 105 ) ( 106 ) ( 107 ) ( 108 ) ( 109 ) ( 10 a ) ( 10 b ) ( 10 c ) ( 10 d ) ( 10 e ) ( 10 f ) (110 ) (111 ) ( 112 ) ( 113 ) ( 114 ) ( 115 ) ( 116 ) ( 117 ) ( 118 ) ( 119 ) ( 11 a ) ( 11 b ) ( 11 c ) ( 11 d ) ( 11 e ) ( 11 f ) ( 120 ) ( 121 ) ( 122 ) ( 123 ) ( 124 ) ( 125 ) ( 126 ) ( 127 ) ( 128 ) ( 129 ) ( 12 a ) ( 12 b ) ( 12 c ) ( 12 d ) ( 12 e ) ( 12 f ) ( 1 d0 ) ( 1 d1 ) ( 1 d2 ) ( 1 d3 ) ( 1 d4 ) ( 1 d5 ) ( 1 d6 ) ( 1 d7 ) ( 1 d8 ) ( 1 d9 ) ( 1 da ) ( 1 db ) ( 1 dc ) ( 1 dd ) ( 1 de ) ( 1 df ) ( 1 e0 ) ( 1 e1 ) ( 1 e2 ) ( 1 e3 ) ( 1 e4 ) ( 1 e5 ) ( 1 e6 ) ( 1 e7 ) ( 1 e8 ) ( 1 e9 ) ( 1 ea ) ( 1 eb ) ( 1 ec ) ( 1 ed ) ( 1 ee ) ( 1 ef ) ( 1 f0 ) ( 1 f1 ) ( 1 f2 ) ( 1 f3 ) ( 1 f4 ) ( 1 f5 ) ( 1 f6 ) ( 1 f7 ) ( 1 f8 ) ( 1 f9 ) ( 1 fa ) ( 1 fb ) ( 1 fc ) ( 1 fd ) ( 1 fe ) ( 1 ff ) . . . rom fonts figure 8 ? 3 . * page 1 including 256 standard rom font configuration
NT68275 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 figure 9 - 1 . 12 * 18 dots font 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 figure 9 - 2 . bordering effect figure 9 - 3 . shadowing effect
nt682 75 30 osd screen po sition: figure 10 be low illustrates the position of all display characters on the screen relative to the leading edge of horizontal and vertical fly - back signals. u raster hflb vflb osd screen 15 30 ( 30*12 =360 dots ) hpos *6 + 49 dots vpos *4 + 1 lines vflb hflb t t figure 10 . osd screen position
NT68275 31 osd display format : osd screen 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 double height double width 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 line expanded = 22 lines & double width line expanded = 22 lines & double height figure 11 . osd display format
NT68275 32 osd window setting: column start address row end address row start address 15 30 window1/2/3/4 area row start/end control register: row15 /column 0/3/6/9 column start control register: row15 /column 1/4/7/10 column end control register: row15 /column 2/5/8/11 window color control register: row15 /column 2/5/8/11 column end address figure 12 . window size setting window area width height height width width adjustment control register : row15 /column 21 height adjustment control register : row15 /column 22 shadow colorselection control register : row15 /column 19 note : width adjustment units : pixels height adjustment units : h lines osd screen area ( 15 row by 30 column ) figure 1 3 . window shadowing setting
NT68275 33 characters? programm able height: tab 9 . line expanded example 1: if user set s crh0 = 1 , crh2= 1 , crh3= 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh0 ! crh2 ! ! ! ! crh3 ! ! ! ! ! ! ! ! ch4 ? ch 0 <= 18 ! ! ! ! ! ! ! ! ! ! ! ! ! result : 31 lines 18+ 8*crh3+4*crh2 +crh0 ! !! !! !! ! !! !! !! !! !! !! !! ! !! !! !! ! ! example 2: if user set s crh0 = 1, crh 3= 1 , crh4 = 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh0 ! crh3 ! ! ! ! ! ! ! ! crh4 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ch4 ? ch 0 >= 18 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! result : 35 lines 18+17 !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! !! ! example 3: if user set s crh1 = 1, crh3 = 1 , ch5 = 0 , ch6 = 1 line 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 original font ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! crh1 ! ! crh3 ! ! ! ! ! ! ! ! ch4 ? ch0 < 18 ! ! ! ! ! ! ! ! ! ! crh6,5=(1,0) ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! result : 46 lines 18+( 8 * crh3 ) + (2*crh1)+ 18 * 1 !! !!! !! !!! !!! !!! !! !!! !! !!! !! !!! !!! !!! !! !!! !! !!
NT68275 34 multi - color font operation: multi-color font r g b o/p green cyan red figure 1 4 . multi - color font example above, the novatek logo is consisted of four fonts. the r, g, b output channels will send out their corresponding font data and it can then display multiple color s in the same font . when using the multi - color font, it can not be set as black and the bordering and shadowing are not available.
NT68275 35 figure 1 5 - 1 . font code example
NT68275 36 figure 1 5 - 2 . font code example (continued)
NT68275 37 application circuit vcc 5.6 k 12 k 1 m 0.01 uf . . . . . 0.01 uf 5.6 k . . 0.1 uf vcc r g b fbkg pwmclk/int vflb hflb scl sda 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 agnd vco rp avcc hflb nc sda scl dgnd r g b fbkg pwm/ /int vflb dvcc 220 uf 100 pf 100 pf 470 470 470 470 220 100 pf . . . . . . . . . . . . NT68275 application circuit 220 uf 0.1 uf
NT68275 38 package information p - dip 16l outline dimensions unit: inches/mm 1 8 16 d e 1 s a 2 a l c e e a \ 9 b 1 b e 1 base plane a 1 seating plane symbol dimension in inch dimension in mm a 0.175 max. 4.45 max. a 1 0.010 min. 0.25 min. a 2 0.1300.010 3.300.25 b 0.018 + 0.004 0.46 +0.10 - 0.002 - 0.05 b 1 0.060 +0.004 1.52 +0.10 - 0.002 - 0.05 c 0.010 +0.004 0.25 +0.10 - 0.002 - 0.05 d 0.750 typ. (0.770 max.) 19.05 typ. (19.56 max.) e 0.3000.010 7.620.25 e 1 0.250 typ. (0.262 max.) 6.35 typ. (6.65 max.) e 1 0.1 000.010 2.540.25 l 0.1300.010 3.300.25 \ 0~ 15 0~ 15 e a 0.3450.035 8.760.89 s 0.040 max. 1.02 max. note: 1. the maximum value of dimension d includes end flash. 2. dimension e1 does not include resin fins. 3. dimension s includes end fl ash.

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